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FEATURES

LT3740 Wide Operating Range, Valley Mode, No RSENSETM Synchronous Step-Down Controller DESCRIPTIO
The LT(R)3740 is a synchronous step-down switching regulator controller that drives N-channel power MOSFET stages. The controller uses valley current mode architecture to achieve very low duty cycles with excellent transient response without requiring a sense resistor. The LT3740 includes an internal step-up converter to provide a bias 7V higher than the input voltage for the drive. This enables the part to work from an input voltage as low as 2.2V. The XREF pin is an external reference input that allows the user to override the internal 0.8V feedback reference with any lower value, allowing full control of the output voltage during operation, output voltage tracking or soft-start. The LT3740 has three current limit levels that can be chosen by connecting the RANGE pin to ground, open, and input respectively.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. No RSENSE is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners.
Wide VIN Range: 2.2V to 22V Internal Boost Provides 6V Gate Drive Down to 2.2VIN No Sensing Resistor Required Dual N-Channel MOSFET Synchronous Drive Valley Current Mode Control Optimized for High Step-Down Ratio Power Good Output Voltage Monitor 0.8V Reference Three Pin-Selected Current Limit Levels Constant Switching Frequency: 300kHz Programmable Soft-Start Output Voltage Tracking Available in 16-Pin 5mm x 3mm DFN
APPLICATIO S

Notebook and Palmtop Computers, PDA Portable Instruments Distributed Power Systems
TYPICAL APPLICATIO
High Efficiency Step-Down Converter
VIN 3V to 12V 10F
94 92 90
22H
LT3740 SWB BGDP VIN SHDN BIAS TGATE 1
1F
VIN = 3V
M1 HAT2168H 0.9H D1 B320A VOUT 1.8V 10A 100F x3
EFFICIENCY (%)
1 SW SN+ 1 BGATE M2 HAT2165H
88 86 84 82 VOUT = 1.8V 80 VIN = 12V
15k XREF
0.22F VC 20k 1nF SN
-
39pF 105k PGND
15k
0
RANGE GND FB 22pF 80.6k
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Efficiency vs Load Current
VIN = 5V
2
4 6 LOAD CURRENT (A)
8
10
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LT3740
ABSOLUTE
AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW SN
-
10V 22V 32V SWB Voltage ............................................................ 36V Maximum Junction Temperature .......................... 125C Operating Temperature Range (Note 2) ... -40C to 85C Storage Temperature Range .................. -65C to 125C
(Note 1) SN-, BGATE, VC, FB, XREF, PGOOD Voltages ........... VIN, SHDN, SW, Range Voltages .............................. BIAS, TGATE, BGDP, SN+ Voltages ..........................
1 2 3 4 5 6 7 8 17
16 VC 15 FB 14 XREF 13 SHDN 12 PGOOD 11 RANGE 10 VIN 9 SWB
ORDER PART NUMBER LT3740EDHC
PGND BGATE BGDP SN+ SW TGATE BIAS
DFN PART MARKING 3740
DHC PACKAGE 16-LEAD (5mm x 3mm) PLASTIC DFN TJMAX = 125C, JA = 43C/W EXPOSED PAD IS GND (PIN 17), MUST BE SOLDERED TO PCB
Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
PARAMETER Minimum Operation Voltage Maximum Operation Voltage Input Supply Current Feedback Reference Voltage Feedback Voltage Line Regulation FB Pin Input Current Error Amplifier Transconductance Controller Switching Frequency Minimum Off Time Current Limit RANGE = 0V RANGE = Open RANGE = VIN VIN = 2.5V to 22V FB = 800mV VC = 1.2V CONDITIONS
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C, VIN = 5V unless otherwise noted. (Note 2)
MIN

TYP
MAX 22
UNITS V V A mA
2.2 0.6 2.5
SHDN = 0V SHDN = 5V, BIAS = 14V, FB = 1.5V
794
800 0.006 230 380
808
260 25 55 80
300 500 50 80 105 35
330 700 85 115 140
Reverse Current Limit SHDN Voltage to Enable Device SHDN Voltage to Disable Device TGATE On Voltage TGATE Off Voltage BGATE On Voltage BGATE Off Voltage TGATE Rise Time TGATE Fall Time BGATE Rise Time CLOAD = 3300pF CLOAD = 3300pF CLOAD = 3300pF

1.1 0.5 5.5 0.2 5.5 0.2 30 30 50
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mV % nA S kHz ns mV mV mV mV V V V V V V ns ns ns
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ELECTRICAL CHARACTERISTICS
PARAMETER BGATE Fall Time PGOOD Threshold PGOOD Low Voltage PGOOD Current Capacity Internal Boost Switching Frequency Internal Boost Switch Current Limit (BIAS - VIN) in Operation (BIAS - VIN) to Start Controller IPGOOD = 100A CONDITIONS CLOAD = 3300pF
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C, VIN = 5V unless otherwise noted.
MIN

TYP 50 740
MAX 765 0.2
UNITS ns mV V A MHz mA V V
720 500 0.8 360
1 440 7.8 7.2
1.2 520
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.
Note 2: The LT3740E is guaranteed to meet performance specifications from 0C to 85C. Specifications over the -40C to 85C operating temperature range are assured by design, characterization and correlation with statistical process controls.
TYPICAL PERFOR A CE CHARACTERISTICS (TA = 25C, unless otherwise noted)
Transient Response
VOUT 50mV/DIV LOAD STEP 0A TO 10A VIN = 10V, VOUT = 2.5V FIGURE 4 CIRCUIT
IL 5A/DIV
20s/DIV
XREF Pin Start-Up
0 -0.1
IL 2A/DIV
CURRENT SENSING LIMIT (mV)
SS 0.5V/DIV
DVOUT (%)
VO 2V/DIV VIN = 10V, VOUT = 2.5V ILOAD = 3A
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2ms/DIV
UW
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Transient Response
LOAD STEP 0A TO 10A VIN = 5V, VOUT = 1.8V PAGE 17 CIRCUIT VOUT 50mV/DIV
Shutdown Pin Start-Up
SHDN 2V/DIV IL 2A/DIV
VO 2V/DIV
IL 5A/DIV
VIN = 10V, VOUT = 2.5V ILOAD = 3A
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10s/DIV
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2ms/DIV
Load Regulation
200
Current Limit vs Bottom Gate On-Time
VIN = 10V VOUT = 2.5V RS = 12m
180 160 140 120 100 80 60 40 20 0 RANGE = GND
RANGE = VIN RANGE = OPEN
-0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 0 2 RANGE = OPEN 6 4 LOAD CURRENT (A) 8 10
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RANGE = VIN RANGE = GND
30
40 50 60 80 90 70 BOTTOM GATE ON DUTY CYCLE (%)
100
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LT3740 TYPICAL PERFOR A CE CHARACTERISTICS
Shutdown vs Maximum VC
2.0
CURRENT SENSING THRESHOLD (mV) 300 250 RANGE = VIN 200 150 100 50 0 RANGE = GND
1.8 1.6
MAXIMUM VC (V)
1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 0.5 1 1.5 2 SHUTDOWN (V) 2.5 3
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VFB (mV)
PGOOD Threshold vs Temperature
770 760 750 740 730 720 710 -50
1.0
SHDN (V) VFB (mV)
CONTROLLER FREQUENCY (KHz)
-25
0 25 50 TEMPERATURE (C)
Error Amplifier Transconductance vs Temperature
400 390 380
ERROR AMP (s)
7.50 7.45 7.40 7.35
UNDERVOLTAGE LOCKOUT VIN (V)
370 360 350 340 330 320 310 300 -50 -25 0 25 50 TEMPERATURE (C) 75 100
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BIAS-VIN (V)
4
UW
75
(TA = 25C, unless otherwise noted) Feedback Reference Voltage vs Temperature
810 808 806 804 802 800 798 796 794 792
VC vs Current Sensing Threshold
RANGE = OPEN
1
1.1 1.2
1.3
1.4 1.5 VC (V)
1.6
1.7
1.8
790 -50
-25
0 25 50 TEMPERATURE (C)
75
100
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Shutdown Threshold vs Temperature
1.2 1.1 320 315 310 305 300 295 290 285 -25 0 25 50 TEMPERATURE (C) 75 100
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Switching Frequency vs Temperature
0.9 0.8 0.7 0.6 0.5
100
0.4 -50
280 -50
-25
0 25 50 TEMPERATURE (C)
75
100
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BIAS-VIN to Enable Controller vs Temperature
3.0 2.5 2.0 1.5 1.0 0.5
Undervoltage Lockout Threshold vs Temperature
7.30 7.25 7.20 7.15 7.10 7.05 7.00 -50 -25 0 25 50 TEMPERATURE (C) 75 100
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0 -50
-25
0 25 50 TEMPERATURE (C)
75
100
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SN- (Pin 1): Negative Current Sensing Pin. Connect this pin to the source of the bottom MOSFET for No RSENSE or to a current sense resistor. PGND (Pin 2): Power Ground. Connect this pin closely to the source of the bottom N-channel MOSFET. BGATE (Pin 3): Bottom Gate Drive. Drives the gate of the bottom N-channel MOSFET. BGDP (Pin 4): Bottom Gate Drive Power Supply. Connect this pin to a voltage source higher than 7V (VIN or BIAS). SN+ (Pin 5): Positive Current Sensing Pin. Connect this pin to the drain of the bottom MOSFET for No RSENSE or to a current sense resistor. SW (Pin 6): Switch Node. Connect this pin to the source of the top N-channel MOSFET and the drain of the bottom N-channel MOSFET. TGATE (Pin 7): Top Gate Drive. Drives the gate of the top N-channel MOSFET to BIAS. BIAS (Pin 8): Top Gate Drive Power Supply. Connect a capacitor between this pin and VIN. SWB (Pin 9): Switch Pin of the Internal Boost. Connect the boost inductor here. VIN (Pin 10): Input Supply Pin. Must be locally bypassed with a capacitor. RANGE (Pin 11): Current Limit Range Select Pin. Ground this pin for 50mV current sense voltage limit. Leave this pin open for 80mV current sense voltage limit. Connect this pin to VIN for current sense voltage limit of 105mV. PGOOD (Pin 12): Power Good Output. Open collector logic output that is pulled low when the FB voltage lower than 720mV. SHDN (Pin 13): Shutdown Pin. Connect to 2.5V or higher to enable device; 0.2V or less to disable device. Also, this pin functions as soft-start when a voltage ramp is applied. XREF (Pin 14): External Reference Pin. This pin sets the FB voltage externally between 0V and 0.8V. It can be used to slave the output voltage during normal operation or the output start-up behavior to an external signal source. Tie this pin to 1V or higher to use the internal 0.8V reference. FB (Pin 15): Feedback Pin. Pin voltage is regulated to 0.8V if internal reference is used or to the XREF pin if voltage is between 0V and 0.8V. Connect the feedback resistor divider to this pin. V C (Pin 16): Error Amplifier Compensation Pin. Connect the external compensation RC to this pin. The current comparator threshold increases with the voltage of this pin. Exposed Pad (Pin 17): Ground. Must be soldered to PCB ground.
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BLOCK DIAGRA
Gm
- -
A2 R S Q Q1
+
VC 16 SHDN 13 RAMP GENERATOR
+
XREF 14
FB 15
-
0.72V
+
11 RANGE RAMP GENERATOR 300KHz OSCILLATOR
PGOOD 12
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VIN 10 SWB 9 7.6V
+
-
A3
+
1.2MHz OSCILLATOR 8 BIAS
7
TGATE
+ - +
gm
-
A1 SWITCH LOGIC
6
SW
4
BGDP
+
VREF 0.80V 3 BGATE
2
PGND
- +
5
SN+
1
SN-
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LT3740
OPERATIO
The LT3740 is a constant-frequency, valley current mode controller for DC/DC step-down converters. At the start of each oscillator cycle, the switch logic is set, which turns on the bottom MOSFET. After a 500ns blanking time, the bottom MOSFET current is sensed and added to a stabilizing ramp, and the resulting sum is fed into the PWM comparator A1. When this voltage goes below the voltage at VC pin, the switch logic is reset, which turns off the bottom MOSFET, and turns on the top MOSFET. The top MOSFET remains on until the next oscillator cycle. The bottom MOSFET current can be determined by sensing the voltage between the drain and source of the MOSFET using the bottom MOSFET on-resistance, or by sensing the voltage drop across a resistor between the source of the bottom MOSFET and ground. The two current sensing pins are SN+ and SN-. The gm error amplifier adjusts the voltage on the VC pin by comparing the feedback signal VFB with the reference, which is determined by the lower of the internal 0.8V reference and the voltage at the XREF pin. If the error amplifier's output increases, more current is delivered to the output; if it decreases, less current is delivered. The LT3740 features an open collector PGOOD signal. When the voltage at FB pin is less than 720mV, the PGOOD output is pulled low by a NPN transistor. The 720mV threshold is independent of the voltage on XREF pin. The small internal step-up converter provides a BIAS voltage about 7V higher than the input voltage VIN for the drive of the top MOSFET. This enables the LT3740 to work from an input voltage as low as 2.2V. The controller starts operation when the BIAS pin is about 7V higher than VIN pin. The voltage supply for the bottom MOSFET drive is provided through the BGDP pin. For VIN lower than 7V, BGDP should be connected to BIAS to get enough drive bias. For VIN higher than 7V, BGDP can be connected directly to VIN to reduce power loss. Grounding the SHDN pin turns both the internal step-up converter and the controller off. The SHDN pin can also be used to implement an optional soft-start function.
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Start-Up and Shutdown During normal operation, when the feedback voltage is above 720mV, the LT3740 operates in forced continuous mode. When the feedback voltage is below 720mV, either during the start-up or because an external reference is applied, a zero current detect comparator is enabled to monitor the on-state bottom MOSFET current. When the current reaches zero, both the top and bottom MOSFETs are turned off, resulting in discontinuous operation. During the time that both top and bottom MOSFETs are off, no current signal is fed into the LT3740. Only the stabilizing ramp is fed into the PWM comparator to decide the next turn on of the top MOSFET. The LT3740 uses the SHDN pin to implement one of the two different startup schemes. As shown in the block diagram, the VC pin is clamped to SHDN pin through a PNP transistor. If the SHDN pin is slowly ramped up, the VC pin will track it up proportionally. As the VC pin voltage is compared to the current signal at comparator A1, this will, in turn, slowly ramp up the switching current. The tracking capability built into XREF can be used to implement another startup scheme. If less than 0.8V is applied to XREF , the LT3740 will use this voltage as the reference for regulation. Slowly ramping up the voltage at XREF forces the output to increase slowly, which limits the start-up current, as shown in Typical Performance Characteristics. A sharp SHDN signal is recommended to shut down the LT3740. If SHDN slowly ramps down, the VC signal will be dragged low for a considerable period of time before SHDN reaches its turn-off threshold. During this period of time, the output voltage could still be in regulation and the circuit operates in forced continuous mode. A low VC voltage will result in large bottom MOSFET on-time, which may cause a reverse inductor current that pumps the energy from the output to the input. If there is another supply at the output or the output has a big capacitor, the input voltage could overshoot, and may cause overvoltage damage to certain devices.
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APPLICATIO S I FOR ATIO
Current Sensing Range Inductor current is determined by measuring the voltage across a sense resistance - either the on-resistance of the bottom MOSFET or an external sensing resistor. The maximum current sense threshold has three steps that are selected by the RANGE pin. The current sense threshold voltage without slope compensation is shown in Table 1. This is the value for high duty cycle operation.
Table 1. Current Sensing Thresholds
RANGE Pin Ground Open VIN Current Sensing Threshold 50mV 80mV 105mV
Slope Compensation The LT3740 has a compensation slope to stabilize the constant-frequency valley mode operation. The slope compensation signal increases with the bottom gate duty cycle, which results in a current sense threshold voltage change with duty cycle as shown in the figure in Typical Performance Characteristics. The three current limit levels correspond to three compensation slopes. The compensation slope needs to overcome the difference between the up and down slope of the inductor current to avoid sub-harmonic oscillation. Maximum compensation slope is required for high input voltages, where the duty cycle is small. The compensation slope can only be selected by the RANGE pin. In the case of insufficient compensation slope, the inductor ripple current or the sensing resistance needs to be reduced.
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Reverse Current Limit Because the LT3740 operates in forced continuous mode when the feedback voltage is higher than 720mV, the inductor current can go negative on occasion, such as light load, shutting down with a slow SHDN signal, large load step-down transient response, or the output voltage being pulled up by some other power supply. The LT3740 has a reverse current comparator to limit the reverse current. During the on-time of the bottom MOSFET, when (V SN+)-(VSN -) reaches 40mV, the comparator is triggered and turns off the bottom MOSFET. When operated under light load, the inductor current goes negative every cycle. The design of the inductor current ripple and the sensing resistor need to ensure that the reverse current comparator is not triggered during normal operation. Power MOSFET Selection The LT3740 requires two external N-channel power MOSFETs, one for the top switch and one for the bottom switch. Important parameters for the power MOSFETs are the breakdown voltage V(BR)DSS, threshold voltage V(GS)TH, on-resistance RDS(ON), reverse transfer capacitance CRSS and maximum current IDS(MAX). When the bottom MOSFET is used as the current sense element, particular attention must be paid to the initial variation, the gate-source voltage effect and the temperature characteristics of its on-resistance. MOSFET onresistance decreases as the gate-source voltage increases. The change of BGDP voltage could affect the bottom MOSFET gate voltage. Refer to the MOSFET datasheet for the MOSFET on-resistance corresponding to certain gate voltage. MOSFET on-resistance is typically specified with a maximum value R DS(ON) at 25C. In this case, additional margin is required to accommodate the rise in MOSFET on-resistance with temperature: RDS(ON) = RSENSE/T
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APPLICATIO S I FOR ATIO
The T term is a normalization factor (unity at 25C) accounting for the significant variation in on-resistance with temperature, typically about 0.4%/C as shown in Figure 1. For a maximum junction temperature of 100C, using a value T = 1.3 is reasonable.
2.0 VGS = 10V ID = 14A
rDS(ON) - ON RESISTANCE (NORMALIZED)
1.6
1.2
0.8
0.4
0 -50 -25 0 25 50 75 100 125 150 TJ - JUNCTION TEMPERATURE (C)
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Figure 1. MOSFET RDS(ON) vs. Temperature
LT3740 SW
Gate Drives The top gate drive power is provided by BIAS which is about 7.6V higher than VIN. The top gate voltage can be as high as 7.6V and can droop to about 5.5V if the on-time is long enough. The bottom gate drive power is provided by the BGDP pin. BGDP needs to be connected to 7V or higher to get enough gate drive voltage for logic-level threshold MOSFETs. BGDP can be connected to VIN, BIAS or an external voltage supply. For input voltages lower than 7V, BGDP should be connected to BIAS to be able to use logiclevel threshold MOSFETs. For VIN higher than 7V, BGDP can be connected to VIN to reduce power loss in the bottom gate drive. For high BGDP voltages, the internal clamp circuit limits the bottom gate drive voltage to about 8V to prevent the gate from overvoltage damage. For the case BGDP is connected to VIN, if VIN voltage ramp up slowly during startup, there will be a considerable period of time that BGDP is below 7V and the circuit is operating. The insufficient voltage on BGDP could cause malfunction of the circuit. One of the solution circuits is shown in Figure 2. The Zener diode and the small MOSFET
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limit the SHDN voltage to be about 6V below VIN. This shuts down the LT3740 for VIN lower than 7V. If VIN can ramp up to 7V quick enough, this circuit is not necessary.
LT3740 VIN MMSZ52312BS 2N7002TA 100k SHDN
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BGDP
Figure 2. Circuit That Prevents Operation for VIN < 7V
For VIN higher than 14V, the high dv/dt at SW node and the strong drive of BGATE can generate extra noise and affect the operation. A resistor RBG of 1-2 between BGATE and the gate of the bottom MOSFET as shown in Figure 3 can effectively reduce the noise.
RBG BGATE M2
PGND
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Figure 3. Noise Reduction for Bottom MOSFET.
The LT3740 uses adaptive dead time control to prevent the top and bottom MOSFET short-through and minimize the dead time. When the internal top MOSFET on signal comes, the LT3740 delays the turn on of TGATE until BGATE is off. When the internal bottom MOSFET on signal comes, the LT3740 delays the turn on of BGATE until the SW node swings down to ground. In the case of small or negative inductor current that SW node cannot swing below ground after TGATE turns off, BGATE will turn on 200ns after TGATE is off.
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APPLICATIO S I FOR ATIO
Choose MOSFET Sensing or Resistor Sensing The LT3740 can use either the bottom MOSFET onresistance or an external sensing resistor for current sensing. Simplicity and high efficiency are the benefits of using bottom MOSFET on-resistance. However, some MOSFETs have a wide on-resistance variation. As discussed previously, the gate-source voltage and the temperature also affect the MOSFET on-resistance. These factors affect the accuracy of the inductor current limit. The inductor saturation current will need enough margin to cover the current limit variation. In the cases where the input voltage supply has sufficient current limit, a wide current limit variation of the controller may be tolerated. As the load increases to reach the input supply current limit, the input voltage corrupts, and limits the total power in the circuit. To reduce the current limit variation, a more accurate external sensing resistor can be used between the bottom MOSFET source and ground. Connect SN+ and SN- pins to the two terminals of the resistor. Power Dissipation The I2R power dissipation in the top and bottom MOSFETs strongly depends upon their respective duty cycles and the inductor current. When operating in continuous mode, the approximate duty cycles for the MOSFETs are:
V DTOP = OUT VIN DTOP = 1- DTOP
The resulting power dissipation in the MOSFETs are: PTOP = DTOP * IL2 * RDS(ON),TOP PBOT = DBOT * IL2 * RDS(ON),BOT If an external sensing resistor is used, the extra power dissipation in the sensing resistor is: PRS = DBOT * IL2 * Rs The power losses in the bottom MOSFET and external sensing resistor are greatest during an output shortcircuit, where maximum inductor current and maximum bottom duty cycle occur.
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Besides I2R power loss, there are transition losses and gate drive losses. The transition losses that increase with the input voltage and inductor current are mainly in the top MOSFET. The losses can be estimated with a constant k = 1.7A-1 as: Transition Loss = k * VIN2 * IL * CRSS * FS The gate drive losses increase with the gate drive power supply voltage, gate voltage and gate capacitance as shown below: PGD,TOP = VBIAS * CGS,TOP * VGS,TOP * FS PGD,BOT = VBGDP * CGS,BOT * VGS,BOT * FS Duty Cycle Limits At the start of each oscillator cycle, the top MOSFET turns off and the bottom MOSFET turns on with a 500ns duty cycle on the top MOSFET. If the maximum duty cycle is reached, due to a dropping input voltage for example, the output voltage will droop out of regulation. The minimum input voltage to avoid dropout is:
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VIN(MIN) =
VOUT 1- tOFF(MIN) * FS
Step-Down Converter Inductor Selection Given the desired input and output voltages, the inductor value and operating frequency determine the ripple current: V V lL = 1- OUT * OUT VIN FS * L Lower ripple current reduces core losses in the inductor, ESR losses in the output capacitors and output voltage ripple. The highest efficiency is obtained with a small ripple current. However, achieving this requires a large inductor. There is a trade off between component size and efficiency. A reasonable starting point is to choose a ripple current that is about 30% of IOUT(MAX). The largest ripple current occurs at the highest VIN. To guarantee that ripple current
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APPLICATIO S I FOR ATIO
does not exceed a specified maximum, the inductance should be chosen according to: V VOUT L = 1- OUT * VIN(MAX ) FS * IL(MAX ) Once the value for L is known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores; instead use ferrite, molypermalloy or Kool M(R) cores. A variety of inductors designed for high current, low voltage applications are available from manufacturers such as Sumida, Panasonic, Coiltronics, Coilcraft and Toko. Schottky Diode D1 Selection The Schottky diode D1 shown in Figure 4 conducts during the dead time between the conduction of the power MOSFET switches. It is intended to prevent the body diode of the bottom MOSFET from turning on and storing charge during the dead time, which can cause a modest (about 1%) efficiency loss. The diode can be rated for about one half of the full load current since it is on for only a fraction of the duty cycle. In order for the diode to be effective, the inductance between it and the bottom MOSFET must be as small as possible, mandating that these components be placed adjacently. Another important benefit of the Schottky diode is that it reduces the SW node ringing at switching edges, which reduces the noise in the circuit and also makes the MOSFETs more reliable. CIN and COUT Selection The input capacitance CIN is required to filter the square wave current at the drain of the top MOSFET. Use a low ESR capacitor sized to handle the maximum RMS current. IRMS IOUT(MAX ) * VOUT * VIN VIN -1 VOUT
This formula has a maximum at VIN = 2VOUT, where:
1 IRMS = * IOUT(MAX ) 2
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This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to derate the capacitor. The selection of COUT is primarily determined by the ESR required to minimize voltage ripple and load step transients. The output ripple VOUT is approximately bounded by: 1 VOUT < lL * ESR + 8 * FS * COUT Since IL increases with input voltage, the output ripple is highest at maximum input voltage. Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering and has the necessary RMS current rating. Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirements. Dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. Special polymer capacitors offer very low ESR but have lower capacitance density than other types. Tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. Aluminum electrolytic capacitors have significantly higher ESR, but can be used in cost-sensitive applications providing that consideration is given to ripple current ratings and long term reliability. Ceramic capacitors have excellent low ESR characteristics but can have a high voltage coefficient and audible piezoelectric effects. The high Q of ceramic capacitors with trace inductance can also lead to significant ringing. When used as input capacitors, care must be taken to ensure that ringing from inrush currents and switching does not pose an overvoltage hazard to the power switches and controller. To dampen input voltage transients, add a small 5F to 50F aluminum electrolytic capacitor with an ESR in the range of 0.5 to 2.
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Current Limit
The maximum inductor current is inherently limited in a current mode controller by the maximum sense voltage. In the LT3740, the maximum sense voltage is selected by the RANGE pin. With valley current control, the maximum sense voltage and the sense resistance determine the maximum allowed inductor valley current. The corresponding output current limit is:
ILIMIT = VSN(MAX ) RS I +L 2
The current limit value should be checked to ensure that ILIMIT(MIN) > IOUT(MAX). The maximum sense voltage increases as duty cycle decreases. If MOSFET on-resistance is used for current sensing, it is important to check for self-consistency between the assumed MOSFET junction temperature and the resulting value of ILIMIT which heats the MOSFET switches. In the event of output short-circuit to ground, the LT3740 operates at maximum inductor current and minimum duty cycle. The actual inductor discharging voltage is the voltage drop on the parasitic resistors including bottom MOSFET on-resistance, inductor ESR, external sensing resistor if it is used and the actual short-circuit load resistance. Because of the big variation of these parasitic resistances, the top MOSFET on-time can vary considerably for the same input voltage. In the case of high input voltage and low parasitic resistance, pulse-skipping may happen.
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Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Although all dissipative elements in the circuit produce losses, four main sources account for most of the losses in LT3740 circuits: 1. DC I2R losses. These arise from the on-resistances of the MOSFETs, external sensing resistor, inductor and PC board traces and cause the efficiency to drop at high output currents. The average output current flows through the inductor, but is chopped between the top and bottom MOSFETs. If the two MOSFETs have approximately the same RDS(ON), then the resistance of one MOSFET can simply be summed with the resistances of L and the board traces to obtain the DC I2R loss. For example, if RDS(ON) = 0.01 and RL = 0.005, the loss will range from 15mW to 1.5W as the output current varies from 1A to 10A. 2. Transition loss. This loss arises from the brief amount of time the top MOSFET spends in the saturated region during switch node transitions. It depends upon the input voltage, load current, driver strength and MOSFET capacitance, among other factors. The loss is significant at high input voltages and can be estimated from: Transition Loss = (1.7A-1) * VIN2 * IOUT * CRSS * FS 3. Gate drive loss. The previous formula show the factors of this loss. For the top MOSFET, nothing can be done other than choosing a small CGS MOSFET without sacrificing on-resistance. For the bottom MOSFET, the gate drive loss can be reduced by choose the right BGDP voltage supply. 4. CIN loss. The input capacitor has the difficult job of filtering the large RMS input current to the regulator. It must have a very low ESR to minimize the AC I2R loss and sufficient capacitance to prevent the RMS current from causing additional upstream losses in fuses or batteries.
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LT3740
APPLICATIO S I FOR ATIO
Other losses, including COUT ESR loss, Schottky diode D1 conduction loss during dead time and inductor core loss generally account for less than 2% additional loss. When making adjustments to improve efficiency, the input current is the best indicator of changes in efficiency. If a change is made and the input current decreases, then the efficiency has increased. If there is no change in input current, then there is no change in efficiency. Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to ILOAD*(ESR), where ESR is the effective series resistance of COUT. ILOAD also begins to charge or discharge COUT generating a feedback error signal used by the regulator to return VOUT to its steady-state value. During this recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability problem. The VC pin external components shown in Figure 2 will provide adequate compensation for most applications. For a detailed explanation of switching control loop theory see Application Note 76. Step-Up Converter Inductor Selection The step-up converter in the LT3740 provides a BIAS voltage about 7V higher than the input voltage VIN for the top MOSFET drive and most of the internal controller circuitry. The step-up converter has a current limit of 400mA. An inductor ripple current from 100mA to 200mA is a reasonable design for the converter. For this consideration, a 22H or 47H inductor is recommended for most of the LT3740 applications. Small size and high efficiency are the major concerns. Inductors with low core losses and small DCR at 1MHz are good choices. Some inductors in this category with small size are listed in Table 2.
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Table 2. Recommended Inductors for Step-Up Converter
Part Number LQH3C220 DCR () 0.71 Current Rating (mA) 250 Manufacturer Murata 814-237-1431 www.murata.com Panasonic 714-373-7334 www.panasonic.com Sumida 847-956-0666 www.Sumida.com ELT5KT-220 0.9 420 CDRH3D16-220 CR32-470 0.43 0.97 400 330
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The step-up converter inductor current is the greatest when the input voltage is the lowest. Larger Cgs of the MOSFETs results in large inductor current. Connecting the BGDP pin to the BIAS pin also greatly increases the inductor current. The saturation current of the inductor needs to cover the maximum input current. The step-up inductor current decreases as the input voltage increases. For high input voltages, the step-up converter will begin skipping pulses. Although this will result in some low frequency ripple, the BIAS voltage remains regulated on an average basis, and the step-down controller operation is not affected. For VIN higher than 10V step-up inductor saturation current should be higher than 400mA. For VIN lower than 10V, a lower current rating inductor could be used. The inductor RMS current should be higher than 250mA, and the inductance should not be less than 10H at 400mA. Step-Up Converter Capacitor Selection The small size of ceramic capacitors makes them ideal for the output of the LT3740 step-up converter. X5R and X7R types are recommended because they retain their capacitance over wider voltage and temperature ranges than other types such as Y5V or Z5U. A 1F capacitor is recommended for the output of the LT3740 step-up converter.
Table 3. Recommended Ceramic Capacitor Manufacturers
Manufacturer Taiyo Yuden Murata Kemet Phone 408-573-4150 814-237-1431 408-986-0424 URL www.t-yuden.com www.murata.com www.kemet.com
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LT3740
APPLICATIO S I FOR ATIO
Design Example
As a design example, take a supply with the following specifications: VIN = 7V to 20V (15V nominal), VOUT = 2.5V 5%, IOUT(MAX) = 10A. First, choose the inductor for about 30% ripple current at nominal VIN:
L= 2.5V 2.5V * 1- = 2.3H H (300kHz) * 0.3 * 10 A 15V
Selecting a standard value of 2.0H results in a ripple current of:
IL = 2.5V 2.5V * 1- = 3.47 A (300kHz) * (2H) 15V
Set Range = VIN. At minimum input voltage VIN = 7V, the maximum current sensing voltage is 145mV. Use an external sensing resistor of 12m. The inductor current valley will be clamped to 12A. The ripple current at VIN = 7V is 2.68A, there is about 33% of margin for the 10A load current to cover the maximum current sensing voltage variation. For the case of using MOSFET on-resistance for current sensing, choosing a Si4840 (RDS(ON) = 0.008 (NOM) 0.0095 (MAX) for VGS = 7V, JA = 40C/W) yields a nominal sense voltage of: VSN(NOM) = (10A)(1.3)(0.0095) =123mV To check if the current limit is acceptable, assume a junction temperature of about 55C above a 70C ambient with 125C = 1.5:
ILIMIT = 145mV 2.68 A + = 11.5A 1.5 * 0.0095 2
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Double check the assumed TJ in the MOSFET at VIN = 7V with maximum load current: PBOT = DBOT * IL2 * RDS(ON),BOT
2.5V 2 PBOT = 1- * (10 A ) * 1.5 * 0.0095 = 0.92W 7V
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Double check the assumed TJ in the MOSFET: TJ = 70C + (0.92W)(40C/W) = 107C The power dissipation in the bottom MOSFET increases with input voltage. For VIN = 20V,
2.5V 2 PBOT = 1- * (10 A ) * 1.5 * 0.0095 = 1.25W 20 V
Double check the assumed TJ in the MOSFET: TJ = 70C + (1.25W)(40C/W) = 120C Choose a Si4840 (CRSS = 200pF) for the top MOSFET and check its power dissipation at maximum load current with 100C = 1.3:
PTOP = 2.5V 2 * (10 A ) * 1.3 * 0.0095 + 17 * (20 V)2 * 20 V 10 A * 200pF * 300kHz = 0.15W + 0.41W = 0.56 W
TJ = 70C + (0.56W)(40C/W) = 92C This analysis shows that careful attention to heat sinking will be necessary in this circuit. Check the reverse current comparator margin. The maximum ripple current happens at maximum input voltage:
IL(MAX ) = 2.5V 2.5V * 1- = 3.65A 300kHz * 2H 20 V
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LT3740
APPLICATIO S I FOR ATIO
RS * IL(MAX ) 2 = 12m *
At no load, the maximum reverse current voltage is:
3.65A = 22mV 2
Which is adequately lower than the 35mV reverse current comparator threshold. CIN is chosen for an RMS current rating of about 5A at 85C. The output capacitors are chosen for a low ESR of 0.005 to minimize output voltage changes due to inductor ripple current and load steps. The ripple voltage will be only: VOUT(RIPPLE) = IL * (ESR) = (3.47A)(0.005) = 17mV
L2 22H SWB VIN RANGE SHDN 100k XREF 1F 100k
PGOOD VC
100k 18pF 100pF GND FB 10k
Figure 4. Design Example: 2.5V/10A Output
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However, a 0A to 10A load step will cause an output change of up to: VOUT(STEP) = ILOAD * (ESR) = (10A)(0.005)= 50mV An optional 100F ceramic output capacitor is included to minimize the effect of ESL in the output ripple. For the step-up converter, at VIN = 7V, step-up inductor current is about 27mA. Choose a 22H inductor and a 1F output capacitor. The complete circuit is shown in Figure 4.
LT3740 BGDP BIAS TGATE SW M1 Si4840 L1 2.0H 680F 4V x 2 VOUT 2.5V 10A 100F 6.3V CB 1F VIN 7V to 20V CIN 100F 35V BGATE PGND SN+ SN- RS 12m 21k M2 Si4840 D1 6CWQ03FN
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LT3740
APPLICATIO S I FOR ATIO
PC Board Layout Considerations
As with all switching regulators, careful attention must be paid to the PCB board layout and component placement.
Place the power components close together with short and wide interconnecting trances. The power components consist of the top and bottom MOSFETs, the inductor, CIN and COUT. One way to approach this is to simply place them on the board first. Similar attention should be paid to the power components that make up the boost converter. They should also be placed close together with short and wide traces. Always use a ground plane under the switching regulator to minimize interplane coupling.
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Minimize the parasitic inductance in the loop of CIN, MOSFETs and D1 which carries large switching current. Use compact plane for switch node (SW) to improve cooling of the MOSFETs and to keep EMI low. Use planes for VIN and VOUT to maintain good voltage filtering and to keep power losses low. Unused areas can be filled with copper and connect to any DC node (VIN, VOUT, GND) Place CB close to BIAS pin and input capacitor. Keep the high dv/dt nodes (SW, TG, BG, SWB) away from sensitive small signal nodes.

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LT3740
TYPICAL APPLICATIO S
High Efficiency Step-Down Converter
VIN 7V to 20V LT3740 SWB BGDP VIN SHDN 15k XREF BIAS 1 TGATE 1 SW SN
+
10k VC 16k 1500pF 22pF
EFFICIENCY (%)
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22H
20F 1F M1 HAT2168H 3.4H D1 B340A VOUT 3.3V 10A 2k 100F x3
1 BGATE 0.47F SN
-
M2 HAT2165H
22pF 255k
PGND
RANGE GND FB 80.6k
3740 TA02a
Efficiency vs Load Current
98 96 94 92 90 88 86 84 82 VOUT = 3.3V 80 0 2 6 4 LOAD CURRENT (A) 8 10
3740 TA02b
VIN = 7V VIN = 15V VIN = 20V
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LT3740
TYPICAL APPLICATIO S
2.5V/10A
22H SWB VIN SHDN 10k XREF
1F 10k VC 7.5k RANGE GND 680pF 22pF FB SN- PGND
EFFICIENCY (%)
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LT3740 BGDP BIAS 1 TGATE
1F
VIN 4V to 15V 22F x2 M1 HAT2168H 1.05H D1 B340A VOUT 2.5V 5.1k 100F x3
1 SW SN
+
1 BGATE
M2 HAT2165H
47pF 100k
46.4k
3740 TA03a
EFFICIENCY
96 94 92 90 88 86 84 82 VOUT = 2.5V 80 0 2 4 6 LOAD CURRENT (A) 8 10
3740 TA03b
VIN = 4V VIN = 15V
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LT3740
PACKAGE DESCRIPTIO
3.50 0.05
1.65 0.05 2.20 0.05 (2 SIDES) PACKAGE OUTLINE 0.25 0.05 0.50 BSC 4.40 0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 5.00 0.10 (2 SIDES) R = 0.20 TYP 3.00 0.10 (2 SIDES) PIN 1 TOP MARK (SEE NOTE 6) 8 0.200 REF 0.75 0.05 4.40 0.10 (2 SIDES) BOTTOM VIEW--EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-1) IN JEDEC PACKAGE OUTLINE MO-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 1 0.25 0.05 0.50 BSC 1.65 0.10 (2 SIDES) PIN 1 NOTCH
(DHC16) DFN 1103
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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DHC Package 16-Lead Plastic DFN (5mm x 3mm)
(Reference LTC DWG # 05-08-1706)
0.65 0.05 R = 0.115 TYP 9 16 0.40 0.10 0.00 - 0.05
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LT3740
TYPICAL APPLICATIO
15k XREF
10k VC 16k 1500pF 22pF
RELATED PARTS
PART NUMBER LTC1778 LTC1876 LT3430/LT3431 LTC3708 LTC3728L LTC3778 LTC3824 DESCRIPTION No RSENSE, Step-Down Synchronous DC/DC Controller 2-Phase, Dual Synchronous Step-Down Switching Controller Monolithic 3A, 200kHz/500kHz Step-Down Switching Regulator No RSENSE, Dual, 2-Phase, Synchronous DC/DC Controller Dual, 2-Phase Synchronous Step-Down Controller Wide Operating Range, No RSENSE Step-Down Controller COMMENTS VIN: 4V to 36V, Fast Transient Responds, Current Mode, IOUT 20A Current Mode; 20A per Channel VIN: 5.5V to 60V, 0.1 Saturation Switch, 16-Lead SSOP Package VIN: 4V to 36V, Current Mode, Up/Down Tracking, Synchronizable VIN: 4V to 36V, 550kHz, PLL: 250kHz to 550kHz Single Channel, Separate VON Programming
High Voltage, Wide Input Range, Step-Down Controller With Low IQ VIN: 4V to 60V, IQ = 40A, 100% Duty Cycle, 2A P-Channel Gate Drive, 10-Pin MSOP
20 Linear Technology Corporation
(408) 432-1900
1630 McCarthy Blvd., Milpitas, CA 95035-7417
FAX: (408) 434-0507 www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2006
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High Efficiency Step-Down Converter
22H VIN 7V to 20V LT3740 SWB BGDP VIN SHDN BIAS 1 TGATE 1 SW SN+ 1 BGATE 0.47F SN
-
20F 1F M1 HAT2168H 3.4H D1 B340A VOUT 3.3V 10A 2k 22pF 255k 100F x3
M2 HAT2165H
PGND
RANGE GND FB 80.6k
3740 TA04
3740f LT 1106 PRINTED IN USA

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